1. Field of the Invention
The invention relates generally to integrated circuits, and in particular to function blocks for use in integrated circuits such as gate arrays.
2. Related Art
Gate arrays are popular among integrated circuit (IC) designers as a generally economical way of customizing ICs to obtain application specific integrated circuits. Gate arrays are generally composed of a predefined matrix (or array) of configurable transistor blocks or, in general, function blocks, which can be formed into a specified circuit by interconnecting them.
Of great importance to an IC designer in implementing circuit designs with a gate array is the functionality available from the gate array. That is, the IC designer may have circuit designs which include a large number of different combinational functions (e.g., Boolean logic), sequential functions (e.g., flip-flops, latches), and/or memory functions (e.g., SRAM), and the designer would prefer a gate array which efficiently implements a significant majority of his or her design so that the overall design is implemented in the smallest space possible. Since gate arrays are formed of a matrix of function blocks, the functionality available in each gate array will be primarily determined by the function block architecture.
Also important to an IC designer is customization time. Particularly during the design stages, the IC designer wants to obtain a model, or prototype, of his or her designs quickly so that the designs can be tested and used with other circuitry.
One approach to gate arrays is to create a function block with primarily freestanding transistors, that is, transistors that have few, if any, internal connections to one another within the function block. The transistors within such a function block often vary in size and drive capability with respect to one another to aid in achieving various functions. In order to customize a function block with freestanding transistors, routing of connections between the transistors within the function block must be undertaken as specified by an IC designer. There are generally three to five layers of connecting wires formed over the transistor layer, and each layer requires at least two masking steps to form (one step to form vias to the layer below and one step to form connecting wires). Thus, six to ten masking steps must be undertaken to fully customize a gate array of this type. So although this approach allows for circuit flexibility by allowing for implementation of combinational and sequential functions, as well as memory functions, such an approach will bear additional costs due to multiple masking and routing steps. In addition, because of the multiple masking steps required, production time for customizing the gate array can be considerable.
A second approach to gate arrays, and one having a more rapid customization time, is field programmable gate arrays (FPGAs). The function block configuration in an FPGA is often composed of a fixed circuit of multiplexers and other logic gates and is usually arranged such that varying the input signals to the function block will form various useful functions. Thus, to customize a gate array, an IC designer can specify signals to be coupled to the inputs and outputs for each function block.
FPGA customization time tends to be more rapid than other types of gate arrays because the transistor layer and all connection layers (all vias and wires) are fixed. Also fixed and in between the function blocks in the matrix is an interconnect structure formed of a plurality of intersecting wires. At each intersection is either a fuse or a programmable RAM bit. Thus, to program function block functionality (i.e., to control input signals to each function block), either a fuse is stressed to melt and form a connection at the intersection, or a RAM bit is programmed to form this connection. Since the entire FPGA structure is fixed by the manufacturer, no additional mask steps are required and FPGA programming can actually be done by the IC designer with equipment and software at his or her own place of business. Commonly, an IC designer will specify a function (often from a library) which the designer wishes the function block to perform and the signals to be coupled to function block inputs and outputs are then determined and programmed by software.
Despite rapid and easy customization, FPGAs currently available have drawbacks. First, FPGAs are often used in intermediate design steps for test purposes, but cannot often be used in a final product: because of the nature of the FPGA interconnect structure, an FPGA often will not meet the performance expectations of the final product (e.g., timing) and thus has only limited use in test situations.
Second, few, if any, FPGA manufacturers have developed a function block architecture which can fully support the functionality (e.g., combinational, sequential, and memory functions) required by an IC designer. Almost all FPGA producers produce function blocks capable of implementing a variety of combinational circuits (e.g., Boolean function). A few FPGA suppliers in addition to providing circuits capable of combinational logic, will also provide distinct function blocks for sequential logic (e.g., flip-flops, latches) spaced periodically throughout the FPGA array. While providing the designer with periodic function blocks for sequential function support is helpful, these sequential function blocks may not be in an ideal location with respect to other function blocks (e.g., those supporting combinational functions), may not occur often enough to adequately support IC designs, and particularly may be less than ideal with respect to routing, timing, and other placement issues.
Other FPGA providers provide function blocks which can support both combinational and sequential functions. However, these function blocks are usually designed so that the circuitry supporting each of these function types is separate and distinct within the function block. While providing more options to the designer, this approach will significantly limit gate arrays in size since each function block takes up considerably more space in accommodating distinct circuitry to support each function type. Nonetheless, most FPGA providers using this approach still tend to only place function blocks containing both combinational and sequential logic at periodic intervals throughout the array.
As IC designers create more and more complex IC designs, they are demanding more functional capabilities from gate arrays while further demanding that customization time remain low, that gate array die size remain small, and that device reliability remain high. So, although available gate arrays allow some flexibility to the IC designer, improved architectures for gate arrays are always desirable. Particularly desirable is any architectural design that allows increased flexibility and functionality while reducing customization time.
In order to overcome the problems discussed above, an improved gate array function block architecture is disclosed. The disclosed function block architecture is a fixed, compact circuit, which allows the function block to be configured by input signals to perform combinational, sequential, or memory functions. Moreover, the function block is designed to support tri-state driver, buffering, clock distribution, and other functions necessary for circuit designs implemented with a gate array. Further, gate array customization requires only minimal masking steps to form connections between the function blocks.
The function block architecture in accordance with the invention is divided into three modules: two computational modules and a communication module. Each computational module includes a plurality of inputs and a logic circuit configurable to operate in one of multiple modes of operation; and an output. The multiple modes of operation include a combinational mode of operation and a sequential mode of operation. Some embodiments of the invention further include a memory mode of operation, as well as mixed modes of operation. The logic circuit is configured to operate in one of the multiple modes of operation by applying a set of input signals to the plurality of inputs.
The logic circuit includes a first bit storage unit, which is selectively configurable to store a first bit, and a second bit storage unit, which is selectively configurable to store a second bit. When the logic circuit is in a combinational mode of operation, the first bit storage unit and the second bit storage unit are configured to operate as combinational logic, which, in one embodiment, may be a buffering function. When the logic circuit is in a sequential mode of operation at least one of the first bit storage unit and second bit storage unit are configured to store a bit. In addition, in certain embodiments of the invention, the bit storage units can be configured to be accessed either serially, in one mode of operation, or directly, in a second mode of operation.
Each communication module includes a second plurality of inputs; a second logic circuit configurable to operate in one of second multiple modes of operation; and an output. The multiple modes of operation for the communication module include a tri-state driver mode of operation, a buffer mode of operation, and a clock distribution mode of operation. One of the second plurality of inputs is for receiving an input signal in each of the tri-state driver, buffer, and clock distribution modes of operation. The output from the communication module is for carrying an output signal from each of the tri-state driver, buffer, and clock distribution modes of operation. The second logic circuit is configured to operate in one of the second multiple modes of operation by applying a second set of input signals to the second plurality of inputs.
In one embodiment of the invention, the second logic circuit includes a multiplexer and a tri-state inverter. In a second embodiment, the second logic circuit includes a tri-state buffer.
A function block in accordance with the invention is advantageous in that it is a highly flexible circuit which is relatively small in size, thereby allowing more complicated and larger circuit designs to be implemented on a gate array.
A function block in accordance with the invention is further advantageous in that the function block internal connections are fixed, allowing faster customization time and fewer production errors.
A function block in accordance with the invention is further advantageous in that it utilizes one circuit, including the same output lines and input lines, for all modes of operation, allowing a smaller function block size.
A block in accordance with the invention is further advantageous in that it provides drivers and buffers at regular and useful intervals.
A gate array in accordance with the invention is further advantageous in that clock skew due to clock distribution and clock gating can be minimized.
A gate array in accordance with the invention is also advantageous in that it allows testing of hard to test circuitry, including internally generated clocks.
Other advantages of a gate array in accordance with the invention will be clear to those of skill in the art upon review of the following detailed description.